74AUP2G79 Datasheet | NXP Semiconductors

.. Low-power dual D-type flip-flop; positive-edge trigger Rev. 02 - 19 March 2008 Product data sheet 1. General description The 74AUP2G79 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS patible TTL families. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. The 74AUP2G79 provides the dual positive-edge triggered D-type flip-flop. Information on the data input (n D) is transferred to the n Q output on the LOW-to-HIGH transition of the clock pulse (n CP). The n D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. 2. Features I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I plies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114E Class 3A exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101-C exceeds 1000 V I Low static power consumption; ICC = 0.9 µA (maximum) I Latch-up performance exceeds 100 m A per JESD78 Class II I Inputs accept voltages up to 3.6 V I Low noise overshoot and undershoot < 10 % of VCC I IOFF circuitry provides partial Power-down mode operation I Multiple package options I Specified from - 40 °C to +85 °C and - 40 °C to +125 °C .. NXP Semiconductors Low-power dual D-type flip-flop; positive-edge trigger 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP2G79DC...